MCQ's from moaz file
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How many stages are in the pipelined version of SRC? Name them…(3)
Write the structural RTL for the call instruction for the uni data path implementation?
Call ra, rb(5)
Q - Difference between Memory Address Register and Memory Buffer Register? [2 Marks
Q2. What do you know about Machine Exception? (2 Marks)
Which register holds the address of the next instruction to be executed in the processor?(3)
types of Machine Exception explain any two(5)
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Q.No1(2 marks)
compare unibus implementation of FALCON-A with that of SRC with respect to number of bits of PC and IR.
Q.No2.
In which stage of pipe liningthe effective memory address is calculated?
Q.NO3(3 marks)
Rewrite in SRC
Step
RTL
T0-T2
Instruction fetch
T3
A←R[rb]
T4
C←A-[rb]
T5
R[ra] ←C
Q.no4(3 marks)
Two features of reset operation.
Q.no.5(5 marks)
write structural RTL
call ra,rb
Q.No6(5 marks)
Identify the hazard and how to resolve
200:shlr6,r3,5
204:str r7,30
208:sub r2,r4,r5
(sorry at 210 there was also an instruction, missed that )
212:addr1,r2,r3
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